Shifting registers



June 13, 1961 a. L. CLAPPER 2,988,701

SHIFTING REGISTERS Filed Nov. 19, 1954 7 Sheets-Sheet 1 FIG. I

INVENTOR. OUTPUT P I8 2s--: GENUNG CLAP ER l l 1 l 1 l I BY I 3'8 1 m/ ATTORNEY June 13, 1961 G. L. CLAPPER.

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GENUNG L. CLAPPER OUTPUT OUTPUT T2 ATTORNEY June 13, 1961 G. L. CLAPPER 2,988,701

SHIFTING REGISTERS Filed Nov. 19, 1954 7 Sheets-Sheet 4 FIGJO I RSR INVENTOR.

GENUNG L. CLAPPER ATTORNEY June 13, 1961 G. L. CLAPPER 2,988,701

SHIFTING REGISTERS Filed Nov. 19, 1954 7 Sheets-Sheet 5 30, IL 99 FIG. I2 WAVE 25 |2| 125v CLAMP GEN.

SHIFTING REGISTER INVENTOR.

GEN UNG L. CLAPPER ATTORNEY June 13, 1961 G. L. CLAPPER SHIFTING REGISTERS 7 Sheets-Sheet 6 Filed NOV. 19, 1954 FIG. l4

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INVENTOR. GENUNG L CLAPPER A TTORNEY June 13, 1961 G. L. cLAPPER SHIFTING REGISTERS 7 Sheets-Sheet 7 Filed Nov. 19, 1954 ZOI 7 1% w J 2 m IT 6 T m G mwm H w l. mw m m m F L m FIG.I9

N TH DIMENSION THIRD DIMENSION T S i F SECOND DIMENSION INVENTOR.

GENUNG L CLAPPER A TTORN EY States Patent 2,988,701 SHIFT-IN G REGISTERS Genung L. Clapper, Vestal, N.Y., assignor to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Nov. 19, 1954, Ser. No. 469,895 6 (Cl. 328--37) This invention relates to shifting register circuits.

The shifting register is one of the most useful components of digital computers. Such computers commonly handle data in the form of binary bits, which typically take the form of electrical pulses having one of two distinct current orpotential' values, respectively indicating a binary 0 or a binary l." Such pulses flow through a circuit in a timed sequence, in which the value of a particular bit is indicated by the current or potential in the circuit at a particular interval. If the value of successive bits is the same, then the current or potential does not change during two successive intervals. It is sometimes desirable in suchcomputers to store such bits temporarily, for later use. It is also sometimes desirable to provide serial-to-parallel conversion and parallel-to-serial conversion. By serial-to-parallel conversion is meant that a series of bits following one another in a timed sequence in one circuit are to be split up and sent through separate circuits, either simultaneously or in a timed sequence. Parallel-to-serial conversion is the inverse of that operation. The temporary storage function, the conversion functions, and other functions may be conveniently performed by means of a shifting register circuit.

A shifting register typically comprises a plurality of cascaded triggers. A trigger is a bistable circuit which is tripped from one stable state, representing a binary 0, to another stable state, representing a binary 1," and back to the first state in response to successive input pulses. When such triggers are connected in cascade,

I each trigger of the cascade is connected to receive input pulses from the output of the preceding trigger. In a shifting register, the electrical pulses to be stored or handled in the register are supplied to a data input at the first stage, and a synchronizing input is connected to all the stages. This synchronizing input receives from a suitable generator signals synchronized with the timed sequence of the bits. When a synchronizing signal is passed through that input, then the condition of each trigger in the register is shifted until it assumes the condition of the preceding trigger. The triggers are tripped only in response to the synchronizing signals. The triggers used in shifting registers are typical-1y double-ended, i.e. they have, or may have, two complementary outputs.

Shifting registers present serious problems with respect to the coupling of the successive triggers. Two particular types of coupling arrangements are common. One type -of coupling arrangement employs delay devices between each pair of successive triggers. Such delay devices are in the form of an intermediate storage. When such delay devices are being used, all the triggers in the register that are storing ls are reset to Us by an advance pulse from the synchronizing line. Those triggers being reset produce an output pulse which is stored in the intermediate storage device for a predetermined time, at the end of which it acts on the trigger next in line to shift it from its 0 to its 1" state. This produces the required shift of the register but introduces a delay time necessarily as long as the trigger resolution time (i.e. the time required for a trigger to trip from its 0 to its 1 state or vice versa). Furthermore, the time that each trigger stores the bit must also be at least as long as the trigger resolution time, so that the minimum time between synchronizingor advancing-pulses must be at least twice the resolution time of-the'triggers. While this resolution time 2,988,701 Patented June 13, 1 961 is very short, modern digital computers commonly deal with times of the order of microseconds, and these delay times introduce a definite speed limitation in a shifting register in which the triggers are coupled by delay devices-.- Another comon type of coupling is to provide concurrent advance pulses on two separate synchronizing lines and to gate a selected one or the other of the two pulses into a trigger depending upon the state of the preceding trigger in the register. In such an arrangement, if two adjacent triggers are both storing ls the second trigger will receive a pulse tending to shift it to its 1 state, even though it is already there. Such a system may produce an error if a trigger changes state during the advance pulse. To avoid such errors, the times of the synchronizing pulses must be carefully controlled to avoid confusion with the times at which the incoming binary bit pulses may change.

The conventional shifting registers just described require the triggers to distinguish between the positive-going portions and the negative-going portions of square wave input pulses. Typically, the negative-going portion open ates the trigger, which must not respond to the following positive-going portion. This necessity for polarity discrimination imposes limitations on the design of the triggers which affect adversely the maximum frequency of operation.

Typical triggers used in the prior art registers consist of two translating devices, e.g. vacuum tubes or transistors, with feedback cross-connections between the output of each device and the input to the other. Either device, in turning on, sends through the feedback a pulse elie'c tive to turn the other device off. The time required for a completion of this feedback operation is the resolution time mentioned above. In such triggers, the required polarity discrimination is attained by making the square wave input longer than the resolution time, so that after the tripping of a trigger is initiated by a negative-going pulse, the feedback operation is completed, i.e. the trigger is tripped completely, before the positive-going pulse arrives. In such an arrangement, a small loading of a trigger may be suflicient, especially at high frequencies of operation, to delay the completion of the tripping sufficiently to cause an error.

An object of the present invention is to provide an improved shifting register.

Another object is to provide an improved shifting register circuit operable at higher speed than shifting registers of the priorart.

Another object is to provide a shifting register in which each advance shift is made by shifting only those triggers whose conductive state must be changed to accomplish the shift.

Another object is to provide a shifting register with improved side entry means for parallel-to-serial shifting.

Another object is to provide a shifting register with improved side exit means for serial-to-parallel shifting.

Another object is to provide an improved reversible shifting register.

Another object is to provide a matrix of shifting registers in which shifts may take place either forwardly or at an angle to the forward direction.

The foregoing objects are attained, in the circuits described herein, by providing a gate at the entry to each trigger of a shifting register, said gate including a comparison circuit for checking the condition of that trigger with the condition of the preceding trigger in the register. A bipolar synchronizing pulse is provided. If the preceding trigger is in the same conductive state as the following trigger, then both parts of the bipolar shifting pulse are blocked by the gate. If the two adjacent triggers are not in the same conductive state, then one or the other part of the bipolar pulse is blocked out,

depending upon which trigger is storing a and which is storing a l."

Means are provided for speeding up the operation of the triggers by shortening the trigger resolution time through the use of a clamp circuit which limits the potential swings of the grids. This clamp circuit is also utilized in certain modifications of the invention to provide side entry means for the triggers.

A side exit circuit is provided in certain modifications of the circuit, including a gate for tripping a relay in accordance with the stored data.

In another modification of the invention, each doubleended trigger is provided with two entry gates, one on each end of the trigger, and two outputs. Where one of these entry gates is connected to the preceding trigger in a register chain and the other is connected to the following trigger, then the register is reversible, i.e. data can be fed into it at either end. Alternatively, a number of cascades of these double-ended triggers may be connected in parallel to form a matrix, with one entry gate of each trigger being connected to a laterally adjacent trigger of another cascade and the corresponding output being connected to a laterally adjacent trigger of a third cascade.

Other objects and advantages of the invention will become apparent from a consideration of the following specification and claims, taken together with the accompanying drawings.

In the drawings:

FIG. 1 is a wiring diagram of a single trigger for a shifting register embodying the invention;

FIG. 2 is a graphical illustration of certain potential conditions at various points in the trigger of FIG. 1 during its operation;

FIG. 3 is a somewhat schematic wiring diagram showing a plurality of the triggers of FIG. 1 connected in cascade to form a shifting register;

FIG. 4 is a graphical illustration of a variation of certain potentials in the circuit of FIG. 3 during its operation;

FIG. 5 is a wiring diagram of a modified form of trigger circuit embodying the invention and including a novel side entry;

FIG. 6 is a somewhat schematic wiring diagram showing several of the triggers of FIG. 5 connected in cascade to form a shifting register;

FIG. 7 is a graphical illustration of certain potentials in the circuit of FIG. 6 during its operation;

FIG. 8 is a wiring diagram of a trigger circuit con- 'structed in accordance with the invention, and provided with forward and reverse entries and exits;

FIG. 9 is a somewhat schematic wiring diagram of a plurality of the triggers of FIG. 8 connected to form a reversible shifting register.

FIG. 10 is a somewhat schematic wiring diagram of a plurality of the triggers of FIG. 8 connected to form a shifting register matrix;

- FIG. 11 is a somewhat schematic wiring diagram showing a number of the trigger circuits of FIG. 5 connected to form a shifting register having serial entry and side exit;

FIG. 12 is a wiring diagram of a circuit for providing the bipolar synchronizing pulse required with the shifting registers of the present invention;

FIG. 13 is a wiring diagram of a cathode follower circuit which may be used as a load for the shifting register of the present invention;

FIG. 14 is a wiring diagram of push-pull inverter circuit which may be used as a load for the shifting registers of the present invention;

FIG. 15 is a Wiring diagram of a plate inverter cir cuit which may be used as a load for the shifting registers of the present invention;

FIG. 16 is a wiring diagram of a transistor trigger suitable for use in a reversible shifting register circuit and functionally similar to the trigger of FIG. 8;

FIG. 17 is a somewhat schematic wiring diagram of a self-complementing shifting register;

FIG. 18 is a somewhat schematic wiring diagram of an end to end reversing register; and

FIG. 19 is a somewhat schematic wiring diagram of a single trigger forming one unit of an n-dimensional shifting register matrix.

FIGURE 1 This figure illustrates a trigger circuit which is adaptable to the formation of a shifting register by the connection of a plurality of such circuits in cascade. This trigger circuit includes a pair of triodes 1 and 2 having anodes 1a and 2a, grids 1g and 2g, and cathodes 1c and 2c.

The anode circuits of triodes 1 and 2 are supplied with electrical energy by batteries 3 and 4 through circuits readily traceable in the drawing and including 'a common load resistor 5 connected to the cathodes and separate load resistors 6 and 7 connected to the respective anodes. The anode 1a is connected through a wire 8, a resistor 9 and a parallel capacitor 10 to a junction 9a and thence through a protective resistor 11 to the grid 2g. Anode 2a is connected through a wire 12 and a resistor 13 to the grid 1g. Grid 1g is connected through a resistor 14 to the negative terminal of a biasing battery 15, whose positive terminal is connected to the negative terminal of battery 4. The positive terminal of battery 4 is connected to ground, as indicated at 16. Grid 2g is connected through resistor 11 and a resistor 17 to the negative terminal of biasing battery 15. An output terminal 18 is connected to the wire 8.

Anode 2a is connected through wire 12, a resistor 19, a common junction wire 20 and a resistor 21 to a signal input terminal 22. The common junction wire 20 is connected through a capacitor 23 to grid 1g. A positive synchronizing pulse line 24 is connected through a diode 25 to the common junction wire 20. A negative synchronizing pulse line 26 is connected through a diode 27 to common junction wire 20. It should be noted that the diodes 25 and 27 are oppositely poled with respect to wire 20.

FIG. 2OPERATION OF FIG. 1

The operation of the trigger circuit of FIG. 1 is diagrammatically and graphically illustrated in FIG. 2. In FIG. 2, the line 28 illustrates the variation with time of the potential on the negative synchronizing pulse line 26. Line 29 illustrates the variation .with time of the potential on the positive synchronizing pulse line 24. Line 30 represents a series of incoming signals received at input terminal 22, the particular signals illustrated having been selected arbitrarily for purposes of illustration.

Line 31 shows the variation of potential at the common junction wire 20 in response to the synchronizing signals of lines 28 and 2 9 and the input signals of line 30. Line 32 illustrates the concurrent variation of potential at the grid 1g. Line 33 illustrates the concurrent variation of potential at anode 2a. Line 34 illustrates the concurrent variation of potential at grid 2g, and line 35 illustrates the concurrent variation of potential at the output terminal 18.

In the following description, typical potentials will be mentioned as existing at specific times and places in the circuit, as an aid in describing the operation. It will be readily understood that the invention is not limited to these potentials.

Consider first the conditions in the circuit of FIG. 1 at the time indicated by the vertical line 36 in FIG. 2. Thepotentials on the synchronizing lines 26 and 24'are then +25 and 25 volts, respectively. The'potential at input terminal 22 is the no-signal potential of 25 volts. .The trigger is in its OFF or binary "0 condition, and the triode 2 is OFF.' The potential of anode answer 2a is therefore substantially close to the potential of the positive terminal of battery 3, being. 25 volts; This positive potential is communicated through resistor 13 to grid 1g and opposes the negative'bias of" battery 15 as communicated through resistor 14 sufficiently to hold the triode 1 ON, so that there is a substantial potential drop across resistor 6, with the result that the potential at output terminal 18 is -25 volts. The grid 2g is held at -1 0=0 volts (the cut-01f potential) by the volt age divider action between resistors 6, 9' and 17, so that triode 2 is held off. The grid 1g is held at -88 volts by the voltage divider action throughresistors 7,

, 13 and 14. Since the cut-off potential of the triodes 1 and 2 in this particular circuit is -l00 volts,,triode 1 is ON.

Consider the potential existing at the common junction wire 20. The resistors 19' and 21 are equal, input terminal 22 is at -25 volts and anode 2a is at +25 volts. The potential at junction wire is therefore half-way between these two potentials, or 0 volts.

As illustrated by the line 28 in FIG. 2, the negative synchronizing pulse line 26 supplies to the trigger circuit a series of negative-going pulses. Each of these pulses comprises a shift of the potential of the synchronizing pulse line from volts to 0. The 0 potential is held for a short interval and then the potential returns to +25 volts, where it remains for a longer interval.

The positive synchronizing pulse line 24 supplies an analogous series of positive-going pulses, as indicated by the line 29, in FIG. 2. At the beginning of each of these pulses, the potential of the line 24 shifts from -25 volts to 0. After a brief interval the potential returns to --25 volts and remains there for a longer in terval. Note that the pulses on the two pulse lines 24 and 26 are concurrent.

The triode 1 of FIG. 1 may be regarded as the output tube of the trigger circuit, since the potential of its anode 1a is the potential of the output terminal 18. Triode 2, on the other hand, may be regarded .as the inverse or complementary triode of the trigger circuit. When the trigger is in the OFF or binary 0 condition described above, then its direct output potential (anode 1a) is at -25 volts and its complementary output potential (anode 2a) is at +25 volts. The resistors 19 and 21 and the diodes 2'5 and 27 comprise a gate which compares the output potential of the complementary triode 2 withthe output potential of the preceding stage in the shifting register, which here appears as the potential at input terminal 22.

When the preceding stage in the shifting register is in the same binary 0 state as the circuit of FIG. 1, then the conditions are as indicated at the time 36in FIG. 2.

The input terminal 22 is at -25 volts,-as is the output terminal 18. The complementary output, anode 2a, is

at +25 volts. The common junction 20 is therefore at 0 volts. The synchronizing pulses are received on the hnes 24 and 26 and act through the respective diodes 25 and 27 to clamp the junction 20 at 0 volts. Consequently, under the conditions described, the synchronizing pulses have no effect upon the trigger circuit.

Consider now the effect on the circuit of FIG. 1 when the input terminal 22 shifts from a potential of -25 volts to a potential of +25 volts, as illustrated at the time 37 in FIG 2. Both the input terminal 22 and anode 2a are now at a. potential of +25 volts, so that the potential of common junction 20 tends to swing to +25 volts. This swing is not instantaneous. The junction 20 can not change in potential during a synchronizing pulse, because of the clamping eiicct of the pulses. The swing is further delayed by the time required to charge the capacitor 23, as illustrated by the line 31 in FIG. 2. When the next synchronizing pulse is received, atthe time 38 in FIG. 2, then the negative-goingv synchronizing pulse on line 26 is effective to release the blocking potential across diode 27, and it becomes effective to discharge capacitor 23 and swing the grid 1g more negative. This action follows, as illustrated in line 32 of FIG. 2, shifting the grid 1g below its cut-off potential, and cutting 01f the triode 1. This immediately raises the potential of anode 1a and output terminal 18 to +25 volts. This change is communicated through resistor 9 and capacitor 10 to grid 2g of triode 2, turning the triode 2 ON, and lowering the potential of anode 2a to -25 volts. The trigger circuit is now in the inverse of its original condition, having been tripped to its ON or binary 1 state. It remains stable in this inverse state, as long as the potential at input signal 22 does not change.

At the time indicated by the vertical line 39 in FIG. 2, the input signal at terminal 22 changes from +25 to -25 volts. After the time required to charge capacitor 23, the potential of common junction 20 again shifts, as illustrated by the curve 31 in FIG. 2. Since both input terminal 22 and anode 2a are now at -25 volts, the junction 20 changes its potential to -25 volts. When the next synchronizing pulse is received at the time indicated by the vertical line 40' in FIG. 2, then the positivegoing synchronizing pulse on line 24 is effective to establish through diode 25 a current in the forward direction, which is effective to send a positive-going pulse to grid 1g, turning the tube 1 ON. Anode 1a swings negative, and the change in its potential is transmitted through resistor 9 and capacitor 10 to grid 2g, where it is effective to turn triode 2 OFF. The trigger has now been tripped back to its original binary 0 state.

When the input signal is at +25 volts, indicating that the preceding trigger is ON, and the trigger of FIG. 1 is also ON, then triode 2 is ON, and anode 2a is at -25 volts. The two resistors 19 and 21 again form a voltage divider between +25 and -25 volts, and the common junction wire 20 is again at the intermediate potential of 0 volts. Consequently, when the synchronizing pulses are received, no potential exists across the diodes 25 and 27, no current flows through them, and no signal is received at the grid 1g.

FIGS. 3 AND 4 FIG. 3 illustrates somewhat diagrammatically the. connection of a plurality of trigger circuits of the type shown in FIG. 1 in a cascade to form a shifting register. As illustrated in FIG. 3, each stage of the register comprises a trigger circuit including triodes '1 and 2 and their immediately related circuit elements. These triggers of the register stages are indicated in FIG. 3 by boxes labeled T T T At the entry of each trigger is connected a comparison gate circuit (see FIG. 1) including resistors 19 and 21 and diodes 25 and 27, the latter being connected to the synchronizing pulse lines 24 and 26.

OPERATION OF FIG. 3

It is considered that the operation of each individual stage in the shifting register of FIG. 3 is sufliciently described in connection with FIGS. 1 and 2, above. When a series of signals is received at the input terminal 22 of the first stage, the register responds to set up the various triggers in conductive conditions corresponding to the respective input signals.

At the termination of a particular series of signals or bits, corresponding in number to the number of stages in the register, the last stage (i.e. the one farthest from the input) will be established in a condition which indicates or stores the first binary bit in the series of signals, and the other stages will be indicating or storing corresponding binary bits in the series, with the first trigger stage (i.e. the one nearest the input) storing the last binary bit to be transmitted. There are shown diagrammat-ically in FIG. 3, three stages of a shifting register, numbered respectively 41, 42 and 43. Stages 41 and 42 represent the first two stages in the register and stage 43 represents the last stage.

FIG. 4 illustrates in lines 44 and 45 the negative-going and positive-going synchronizing pulses on lines 26 and 24, respectively. Line 46 represents a series of input signals appearing at the input terminal 22 of the first stage. Line 47 represents the output signals at output terminal 18 of the first stage, and line 48 represents the output signals at output terminal 18 of second stage 42. It may be seen that the signals in each of lines 46, 47 and 48 are shifted one synchronizing interval to the right with respect to the signals in the line above it. This is typical of the operation of a shifting register. On each synchronizing pulse, the signals stored in the various triggers shift one trigger to the right, as viewed in FIG. 3.

A trigger circuit constructed in accordance with FIGS. 1 and 2 has been built and operated satisfactorily with synchronizing pulses of 125 kilocycles.

FIG.

This figure illutrates a modified form of trigger circuit which may be used to construct a shifting register by connecting a plurality of such trigger circuits in cascade. Many of the circuit elements in FIG. 5 correspond to their counterparts in FIG. 1, and where such correspondence exists, the elements have been given the same reference characters in both figures and will not be further described.

One of the principal differences between FIG. 5 and FIG. 1 is that in FIG. 5 the grid biasing arrangement is modified to limit the negative swings of the grids. This modification shortens the resolution time of the trigger to an extent that a shifting register using trigger circuits according to FIG. 5 has been built and successfully operated at a synchronizing pulse frequency of 250 kilocycles.

The other principal difference between the circuit of FIG. 5 and that of FIG. 1 is that provision is made in FIG. 5 for the side entry of signals. In other words, two inputs are provided in the trigger circuit of FIG. 5, one being the input through terminal 22 corresponding to that of FIG. 1, which is the input for signals cascading through the shifting register. The other input allows signals to be fed into the trigger circuit independently of the other triggers in the shifting register.

The grid biasing battery of FIG. 1 is replaced in FIG. 5 by battery 49 having a higher terminal potential. The grid biasing resistors 50 and 51 of FIG. 5 have correspondingly higher resistances. A capacitor 52 is added in parallel with resistor 13, in order to speed the response of the grid lg to changes in potential at the anode 2a. A resistor 53 is connected in series with resistor 5 in the cathode circuits of the triodes 1 and 2. A diode 54 is connected between grid 1g and the common junction of resistors 5 and 53. Two diodes 55 and 56 are connected in series between junction 90 and the common junction 57 of resistors 5 and 53. Protective resistors 58 and 59 are connected in series with the grids 1g and 2g.

A side entry input terminal 60 is connected through a resistor 61 to the junction 62 between diodes 55 and 56. Grid biasing resistor 51 is connected between junction 62 and the negative terminal of battery 49.

A grid biasing resistor 63 connects junction 9a with the negative terminal of battery 49.

The dodes 54, 55 and 56 cooperate with the resistor 53 and battery 5 to clamp the grids 1g and 2g, i.e. to limit their negative swings to 100 volts, being the potential of the negative terminal of battery 4. If the grids tend to swing below this potential, then the diodes 54, 55 and 56 become conductive in their forward directions, immediat'ely raising the grid potentials to those volts. The grids are hence allowed to go to cut-off but can not swing below that value, thereby saving substantial time in the operation of the trigger circuit.

FIG. 6

This figure illustrates the connection of a plurality of the trigger circuits of FIG. 5 to form a shifting register. In order to store n bits, there is provided a shifting register consisting of n+1 triggers. The circuit of FIG. 6 shows five such triggers, identified respectively as SR SR SR SR, and SR All of the triggers except the last have side entry input terminals 60. The shifting register of FIG. 6 may obviously be used in the same manner as the shifting register of FIG. 3, to store binary signals fed into the input terminals 22 of the first trigger SR Alternatively, the shifting register of FIG. 6 may have the binary signals fed into it through the side entry inputs 60, and then may feed the signals out through the output terminal 18 of the trigger SR When the side entries in these triggers are used, the synchronizing pulse lines 26 and 24 are clamped at 0 volts potential, and input signals are fed into the side entry terminals 60.

For example, this mode of operation may be used in translating the data on a punched card into a series of pulses in an electric circuit. Each trigger in the shifting register would then represent one punch location on the card. A signal would be fed or not fed into each trigger, depending upon whether or not a hole was punched at the corresponding card location. Then, after all the triggers are set in 0" or 1 states indicating the data stored on the card, the synchronizing pulse lines 26 and 24 are restored to pulsing operation, whereupon the data stored in the various trigger circuits is fed out through the output terminal 18 of the last trigger. During this feeding out operation, the input terminal 22 of the first trigger should be connected to its no-signal potential (-25 volts). The last trigger SR acts as a gate. That is, it remains at binary 0 during the side entry phase of the operation, so that a side entry can not produce an output signal from the register.

FIG. '7 illustrates graphically an operation such as that just described. The lines 61 and 62 represent the potentials in the synchronizing pulse lines. The line 63 represents the potential at the side entry terminal 60 of trigger SR Line 64 represents the output potential at output terminal 18 of'trigger SR and line 65 represents the output potential at output terminal 18 of trigger n+1- At the time interval indicated by the vertical line 66, the pulse lines 26 and 24 are cleared at 0 volts. Thereafter, at the time 67, a signal is received at side entry terminal 60 of trigger SR This signal is stored in trigger SR as long as the synchronizing pulse lines remain clamped. When the synchronizing pulses start up again, the first synchronizing pulse, at time 68, causes the trigger SR to turn OFF and the trigger SR to turn ON, thereby producing an output pulse from the shifting register. This output pulse terminates at time 69, assuming that the trigger preceding SR was not turned ON during the side entry interval.

It may be seen that the register of FIG. 6 may be used to accomplish a parallel-to-serial conversion, as defined above.

FIG. 8

This figure illustrates another modification of the trigger circuit of FIG. 1, which is adapted for connection with a plurality of other similar trigger circuits to form a reversible shift-ing register. The trigger circuit shown in this figure includes a trigger similar to that of FIG. 1 plus two comparison gates at each side of the circuit, where the trigger of FIG. 1 has only a single comparison gate at its left-hand side. These two gates are hereinafter referred to as the forward and reverse input gates.

Many of the circuit elements of FIG. 8 are similar to those of FIGS. 1 and 5. Where an element corresponds in structure and in function to the corresponding element of FIG. 1 or FIG. 5, the same reference numeral has been used, and that element will not be further described.

In FIG. 8, the diodes 55 and 56 of FIG. 5 have been replaced by a single diode 71, and the circuit elements concerned with the side entry input have been omitted. At the right-hand side of FIG. 8 there is seen the reverse input gate, comprising a resistor 72, a common junction wire 73,. and a resistor having-one terminal connected to-a reverse input terminal 75.

A pair of right-to-left synchronizing pulse lines 76 and 77 are provided, the line: 76 beingthe: negative-going pulse line and line 77 beingthe positive-going pulse line, A diode 78 is connected between line. 77 and common junction wire 73.. A. diode 79' is connected between line 76 and common junction wire. 73.

The. anode 2a. is connected to a reverse output terminalL 80.: Reverse input terminal 75 is: connected to. the reverse output terminal 80 of the next adjacent stage to the. right.

FIG. 9.-

This figure illustrates five; of the triggers of FIG. 8, respectively numbered 81, 82,84 and 85, connected to form a reversible shifting register. When it is desired to run the register of FIG. 9 from left. to right, the reverse synchronizing pulse lines 76 and 77 are clamped at volts, and the operation proceeds. exactly as in the case of FIG. 1.. When it is desired to. reverse the operation of the register, the normal direction synchronizing pulse lines 26 and 24 are clamped at 0. volts. and synchronizing pulses are supplied to the reverse pulse lines 76 and 77. The operation is then analogousto that of FIG. 1, except that the stored signals pass from: right to left rather'than. from left to. right.

FIG. 10

Thisfigure. illustrates ninev of. the trigger circuits of FIG. 8, each of which is identified by the reference RSR, connected to form a. shifting register matrix This matrix comprises threehorizontal rows, numbered respectively 86, 87' and. 88. Each row is a shifting register in itself. Although shown. as consistingof three triggers, it will be readily understood that each horizontal row may consist of. any desired number of triggers. In the circuit of FIG. 10, the reverse input terminal 75. of each trigger is connected to the reverse output, terminal 80 of the trigger immediately below it, and the reverse output terminal 80 of, each trigger is connected to the reverse input terminal 75 of the trigger immediately above.

It, may therefore be seen that in the matrix of FIG. 10, signals may be fed into any one of the registers 86, 87 and 88 from left to right, and that signals may be fed upwardly through the vertical columns of triggers. When feeding signals from left to right, it is necessary that the upward feeding pulse lines be clamped at 0 volts, and when feeding; signals upwardly, the left to right pulse lines must be clamped at 0 volts.

By making the vertical connections diagonal, a diagonal shift of the stored data could be produced.

FIG. 11

This figure illustrates a shifting register constructed in accordance with the. invention and. arranged for a side exit of the stored data. There is shown a shifting register including three triggers, T1, T and T,,, which may be the same as the triggers of FIG. 1. Each of the several trig ger circuits has connected to its output terminal 18 a relay circuit including a relay 89, and a triode 90 having an anode 90a, a grid 90g and a cathode 900. The anode 90a is connected in series with the relay winding 89 and a battery 91. A capacitor 92 is connected between the an ode 90a and the grid 90g. A resistor 93 is connected between grid 90g and output terminal 18 of the trigger. A switch 94 is connected in series with battery 91 and windings of all the relays 89. When signals are being fed into the shifting register circuit, the switch 94 is open, and

the relays 89 are all de-energized. After the signals are stored in the register, the bipolar" pulse lines 26 and 24 are clamped at 0 volts, and the switch 941s closed. The triggers are then effective to bias positively the grids of the tubes 9, for those triggers-which arestoring ls. Consequently, the relays 89 for those triggers are then energized, and may be used to. sendsignal pulsesalong suitable circuits.

10 The circuit described inFlG. l1 accomplishes a serialto-parallel conversion of the type mentioned. above.

The switch 94 may be omitted if, as in the usual case,

the time required to enter data into the register or to clear it, is a very small fraction of the time required to pick up the relay. When the switch 94 is omitted, the relays are picked up selectively by the clamping of the pulse lines 26 and 24. The relays may be dropped by clearing the register.

FIG. 12

The circuit of FIG. 12 provides synchronous bipolar pulses for the pulse lines, and also provides clamping potentials for those lines. As shown in FIG. 12, this circuit includes two input terminals 95 and 96, one connected to a square wave generator diagrammatically indicated at 97 and the other connected to a clamp potential generator diagrammatically indicated at 98. The square wave generator is arranged to provide square wave pulses varying between a no-signal potential of 25 volts and a signal potential of +15 volts. The clamp generator 98 is sim ilarly arranged to provide no-signal potentials of -25 volts and signal potentials of +15 volts, but its output issteady rather than oscillating in a square wave, Input terminal 95 is connected through a diode 99 to a common junction wire 100. Input terminal 96 is connected through a diode 101 to the same junction 100. Two triodes 102 and 103 are provided. Triode 103 is connected as an inverter amplifier for producing negative-going synchronizing pulses. T riode 102 is connected in a cathode follower circuit for producing positive-going pulses.

Triode 102 has an anode 102a, a grid 102g and a cathode 1020. The anode circuit of triode 102 may be traced from the positive terminal of a battery 104 through a re.- sistor 105, anode 102a, cathode 102e, resistors 106, 107 and 108 and batteries 109, 110 and 11 1 in series to the negative terminal of battery 104. Grid 102g is connected through a protective resistor 112 and a resistor 113 to the negative terminal of battery 109. The junction between resistors 112 and 1 13 is connected through a resistor 114 and a parallel condenser 115 to the common junction 100. The same junction between resistors 112 and 113 is connected through a diode 116 to ground. An output terminal 117 is connected to the junction between resistors 106 and 107. A negative clamp for the output terminal 117 is provided including a diode 118, a resistor 119, which is connected to the negative terminal of a battery 110. A capacitor 120 is connected between ground and the common junction of diode 118 and resistor 119. The effect of this clamping circuit is to limit the negative swing of potentials at output terminal 117 to the potential of the negative terminal of battery 110, in the present instance 25 volts. The diode 116 clamps the positive swings of the grid potential, limiting it to 0 volts (ground). The triode 102 operates as a conventional cathode follower circuit, following the positivegoing impulses received from the square wave generator 97, and producing at its output terminal \117 a square wave varying between a no-signal potential of --25 volts and a signal potential of 0 volts.

The circuit of triode 103 is an inverter amplifier circuit. Triode 103 is provided with an anode 103a, a grid 103g and a cathode 1030. The anode circuit of triode 103 may be traced from the positive terminal of battery 111 through a wire 122, a. resistor 123, anode 103a, cathode 103e, a resistor 124, and batteries 109 and 110 in series to the negative terminal of battery 111.

Grid 103g is connected through a protective resistor to a junction 126. Junction 126 is connected through a resistor 127 and a parallel capacitor 128 to the, common junction wire 100. Junction 126 is also connected through a resistor 129 to the negative terminal of a biasing battery 130.

An output terminal 131 is connected. to anode 103a. A diode 132 is connected between output terminal 131 and ground, and serves to clamp the. negative swings. of

aessnor.

the potential of output terminal 131 at ground volts). A capacitor 133 is connected between cathode 1030 and ground.

When the input signal at junction 100' goes positive, it is transmitted to grid 103g and triode 103 conducts, swinging anode 103a and terminal 131 negative. This negative swing is limited to zero volts by diode 132. When the input signal goes negative, triode 103 cuts off, and anode 103a and terminal 131 swing positive to the potential of the positive terminal of battery 111 (+25 volts). FIG 13 This figure illustrates a cathode follower circuit to which the output terminal of a shifting register according to the invention may be connected. The purpose of this circuit is to establish the load on the final trigger of the register at a suitable value, and to translate the output signals received from the register, which vary between 25 volts and +25 volts to a more conventional form of signal, usable in conventional digital computer circuits, and consisting of signal pulses ranging from 25 volts to volts.

The circuit of FIG. 13 comprises a triode 134 having an anode 13411, a grid 134g, and a cathode 1340. The anode circuit of triode 134 may be traced from the positive terminal of a battery 135 through a resistor 136, anode 134a, cathode 1340, resistors 137 and 138, a battery 139, and ground connections to the negative terminal of batery 135. The grid 134g is connected through a junction 140 and a resistor 141 to the final output terminal 18 of a shifting register, which may be any of the shifting registers previously disclosed in this application. Control electrode 134g is provided with a clamp circuit including a diode 142, a resistor 143 and a battery 144 whose effect is to clamp the positive swing of the grid at +15 volts. The junction between diode 142 and resistor 143 is connected through capacitors 145 and 146 to the anode 134a. The common junction of capacitors 145 and 146 is grounded. Junction 140 is also connected through a resistor 147 to the negative terminal of battery 139.

The grid 134g tends to follow the input signals at terminal 18, but is prevented by the clamp circuit mentioned above to swing positively more than 15 volts. The triode 134 operates as a conventional cathode follower, in that its cathode 1340 tends to follow the variations in potentials of the grid 1343. Consequently, the cathode 1340 also swings between volts and +15 volts. This swing is communicated to output terminal 200, which is connected to the common junction of resistors 137 and 138. FIG 14 This figure illustrates a push-pull inverter circuit which may be used in place of the cathode follower circuit of FIG. 13 in instances where a greater power output is desired than is available with the cathode follower circuit. The circuit of FIG. 14 includes two triodes 148 and 149 respectively having anodes 148a and 14911, grids 148g and 149g, and cathodes 1480 and 1490.

The anode circuits of the two triodes 148, 149 are connected in series. The complete circuit may be traced from positive terminal of a battery 162 through a resistor 163, anode 149a, cathode 1490, resistor 154, anode 148a, cathode 1480, resistor 155, anda battery 150 and through ground connections to the negative terminal of battery 162. Grid 148g is connected through a resistor 156 to a junction 157. Junction 157 is connected through a resistor 158 and a capacitor 159 to register output terminal 18. Junction 157 is also connected through a resistor 160 and a battery 161 to ground. Grid 149g is connected through resistor 201 to anode 148a.

The positive swing of the potential of anode 148a is limited by a clamp circuit including a diode 164, a resistor 16S and abattery 166. The common junction of diode 164 and resistor'165 is connected through capacitors 167 and 168 to anode 149a. The common junction of capacitors 167 and 168 is connected to ground.

The negative swings of the potential of cathode 1490 are clamped by a clamp circuit including a diode 153, a resistor 152, and a battery 151. The common junction of diode 153 and resistor 152 is connected through the capacitor 169 and a. capacitor 170 to cathode 1480. The common junction of capacitors 169 and 17 0 is connected to ground. Output terminal 171 is connected to cathode 1490.

The circuit of FIG. 14 inverts the output signals from the shifting register output terminal 18, producing at its output terminal 171 a signal potential +15 volts when a no-signal potential of 25 volts is received at input terminal 18. Conversely, a no-signal output potential of 25 volts is provided at output terminal 171 when a signal potential of +25 volts is received at input terminal 18. The clamp circuit including diode '164 serves to limit the positive swing of the output terminal 171 and the clamp circuit including diode 153 limits its negative swing.

FIG. 15

This figure illustrates another type of inverter circuit which may be used in place of the inverter circuit of FIG. 14, and which is somewhat simpler inthat it uses a single triode 172, having an anode 17211, a grid 172g, and a cathode 1720. The anode circuit of triode 172 may be traced from the positive terminal of a battery 173 through a resistor 174, anode 172a, cathode 1720, a resistor 175, a battery 176, and ground connections to the negative terminal of battery 173. The grid 172g is connected through a resistor 176 to a junction 177. Junction 177 is connected through a resistor 178 and a capacitor 179 to register output terminal 18. Junction 177 is also connected through a resistor 180 and a battery 181 to ground. An output terminal 182 is connected to anode 172a. A capacitor 183 is connected between cathode 1720 and ground.

When the input signal at terminal 18 is +25 volts, triode 172 conducts, producing a potential drop across resistor 174 sufiicient to bring the potential of anode 172a and output terminal 182 down to-25 volts. When the input terminal '18 is at -25 volts, triode 172 cuts off, and output terminal 182 goes to the potential of the positive terminal of battery 173, namely, +15 volts.

"FIGS. 13, 14 and 15 illustrate circuits for connecting the output of a shifting register constructed in accordance with the invention to an ultimate load device. For example, a shifting register might be used with side entry from punched card reading brushes, and a serial output driving a cathode follower used to activate electromagnetic writing units for storing data on a rotating magnetic drum. The particular connecting unit used would be selected to suit the load device. Of course, the register may be used to drive light loads directly.

FIG. 16

Shifting registers according to the invention may be constructed using translating devices of other types than the vacuum tubes illustrated. FIG. 16 illustrates a trigger circuit for a reversible shifting register, similar to that of FIG. 8, except that transistors are used as translating devices in place of the triodes 1 and 2 of FIG. 8. The circuit elements in the forward and reverse gates may be the same in this figure as in FIG. 8, except that the values of the resistors and capacitors'must be changed to correspond with the resistances and capacitances required in the transistor circuits. The transistor trigger circuit generally indicated by the reference character 184 maybe replaced by any other suitable double-ended transistor trigger circuit. For example, the trigger circuit shown in the copending application of Robert A. Henle, Raymond W. Emery, George D. Bruce andv Olin L. MacSorley, Serial No. 459,381, filed September 30, 1954, now

13 United States Patent No. 2.861300, issued November 18, 195 8, may be employed.

As here shown, the trigger circuit,18 4 comprises two point contact transistors 185. and 18.6 respectively having emitter electrodes 185e and 186e,, baseelectrodes 1851; and 186b, and collector electrodes 18,50. and-1860.. The collectors 1:850. and 1860 are. connected respectively through. resistors. 18.7 and. 18.8 to the. negative terminal of a load supply battery 189.. The emitter electrodes 1852 and 1862 are connected together and. thence through a resistor. 198: to ground. The. base electrode185b is connected through. a. resistorv 130 and. a. parallel. condenser 19h to the: collector 186a- Base. 186b is connected through. a. resistor 192. and. a. parallel capacitor 193- to collector 185a. A. resistor 194and a. parallel. diode 195' are connected between base 19512 andv ground. A. resistor 196 and a. parallel. diode 197 are. connected between base 1816b and. ground.

lihe operation. of the. transistor circuit. of" FIG. 16 is generally analogous to that. of. the trigger circuit of FIG. 8; with. modifications. familiar to. those skilled in thetransistor art. For. detailedexplanationof the operation of a trigger circuit of. this type, reference is made to the Henle et al. Patent No. 2,861,200, referred. to above.

FIG; 17

This figure illustrates an arrangement in which a plurality of. the trigger circuits of FIG. 8 are connected to form a self-complementing register. In FIG. 17 there are shown three triggers numbered 201, 202 and 203, each corresponding to the trigger of FIG. 8. In each trigger the. direct. output terminal 18 is connected to the. reverse input terminal 75 of the same trigger. Two sets of pulse lines are provided, the set 26, 24 which produces a left to right shift of stored pulses through the register, and a set of complementing pulse lines 204, 205, which. corresponds to the reverse pulse lines 76, 77 of. FIG. 8.

When it is desired to shift data from left. to right through the register, the complementing pulse lines 204 and 205 are clamped at volts, and the bipolar pulses are supplied as described in connection with FIG. 8, to lines 26and24.

Whenv itis desired to shift the register to produce therein the complement of the data. initially standing in. the register, the lines 26, 24. are clamped. at. 0 volts, and. a bipolar pulse is. supplied to the complementing. lines 204 and 205. For each. pulse. applied. tov the complementing lines 204 and 205, each. trigger will assume the opposite conductive state from that. which. it. previously had.

FIG. 18

This figure illustrates a shifting register including a plurality of'cascaded triggers of the type shown in FIG. 8 and arranged for end-to-end reversal of the data. stored in the register. There are shown in FIG'. 18 four triggers numbered respectively 206, 207; 208 and 209. Triggers 206 and 207 respectively represent the. first and second triggers in the register and' triggers 208 and 209 respectively represent the next to last and last triggers in the register.

Reverse output terminal 80 of trigger 206 is connected through a wire 212 to reverse input terminal 75 of trigger 209; Reverse output terminal 80of trigger 209 is connected through a wire 213 to the reverse input terminal 75 of trigger'206. In a similar manner, the reverse output and input terminals of the second trigger 207 are respectively connected through wires 214 and 215 to the reverse input and output terminals of thenext tolast trigger 208.

Two sets of pulse lines are provided, namely the usual left to right shifting pulse lines 26 and 24 and end-to-endreversing pulse linm 210 and 211, which correspond to the right-to-left lines 76 and 77 of FIG. 8.

Data is entered into the register in the usual manner by clamping the lines, 210 and 211 at 0 volts and supplying pulses to the lines 26 and 24.

When it is desired to reverse the data stored in. the register, the lines 26 and 24 are clamped and a shifting pulse is applied to the lines 210' and 2 11. The data stored in trigger 206 is then shifted to trigger 209 and the data stored in trigger 209 is shifted to 206. Similarly, the data stored in trigger 207 is interchangedwith that in trigger 208. In other words, the data stored in the four triggers is reversed so that, for example, the condition of the first trigger becomes the same as the previous condition of the last trigger. The data stored in each trigger becomes the same as that stored in the corresponding reverse order trigger, i.e. the trigger of the same binary order, counting from the opposite end of the cascade line. It will be readily understood. that the register may consist of any number of triggers, providing corresponding interconnections of the respective input and output terminalsv are provided. If the register has an odd number of triggers, then no connection to the reverse terminals of the center trigger. are necessary, since it will retain its condition during any end-to-end. reversal.

FIG. 19

This figure illustrates a trigger 216 and an arrangement of input gates therefor, which may form one unit of an n-dimensional shifting register. The trigger 216 of this figure comprises that portion of the circuit shown in FIG. 8 which is located between a complementary output junction 210 and a direct input junction 220 on the left hand side and a direct output junction 221 and a reverse input junction 222 on the right hand side. A leftto-right input gate 217 is connected to left-to-right synchronizing lines 26 and 24, which in this circuit. are labeled on the drawing as the west-east synchronizing lines. Each trigger also includes a right-to-left or reverse input gate 218 connected to right-to-left synchronizing lines 76, 77. In this circuit, the right-to-left synchronizing lines are identified as the east-west lines. The circuit elements in the gates 217 and 218 correspond to their counterparts in FIG. 8, and have been given the same reference numerals. Trigger 216 and. gates 217 and 218 correspond fully to the circuit of FIG. 8, which may be described as one. trigger unit of a one-dimensional, bi-directional, i.e. reversible, shifting register. Direct output terminal 18 is connected to the next adjacent trigger in the forward direction, and reverse output ter-- minal is connected to the next adjacent trigger in the reverse direction.

Connected electrically in parallel with the input gates 217 and 218, respectively, is a second. set of input gates 223 and 224. The gate 223 is identified as the northsouth gate and the gate 224 as the south-north gate. The direct output terminal 18 is connected to an adjacent trigger in the south direction from trigger 216- and reverse output terminal 80 is connected to an adjacent trigger in the north direction from trigger 216.

It may be seen that the trigger 216 together with its input gates 217, 218, 223 and 224 may be connected with a plurality of other such triggers to form a two-dimensional matrix, arranged, for example, in a manner generally similar to the matrix of FIG. 10. When so arranged, the data stored in the matrix may be shifted in either direction, in either dimension. Specifically, the data may be shifted from left to right (west-east) or from right to left (east-west). Similarly, it may be shifted from north tosouth, or from south to north. Only one set of synchronizing lines may be energized at one time, and all other synchronizing lines must be clamped, e.g., at 0 volts.

By providing each trigger 216 with two additional input gates 225 and 226, a. plurality of such trigger units may be connected to form a three-dimensional trigger circuit. In each trigger, the input gate 225 is connected. to direct input junction 220 and reverse output junction 219, and the input gate 226 is connected to reverse input junction 222 and direct outpufjunction 221.

By expanding this principle and adding other pairs of forward and reverse input gates, such as gates 227 and 228 of FIG. 19, a matrix may be constructed having n dimensions of storage. A set of synchronizing pulse lines must be provided for each set of input gates in the matrix. It is also necessary that only one set of synchronizing lines be pulsed at any given time, and that all the others be then clamped at volts.

If it is not required that the register be bi-directional in any dimension, then either the forward or reverse input gate for that dimension may be omitted.

Note that even though a plurality of input gates are connected in parallel at each trigger, signal pulses can reach the trigger only through the one input gate whose synchronizing pulse lines are not clamped, so that the parallel input gates do not interfere with each other.

Each of the shifting register arrangements of FIGS. 3, 6, 10, 17, 18 and 19 has utility for at least one specific purpose. They also illustrate the flexibility and versatility of the comparison gate and bipolar synchronizing pulse line arrangement with respect to the construction of shifting registers for a wide range of general and specialized purposes. Triggers may be connected with such gate and pulse line arrangements to form a wide variety of shifting register configurations other than those specifically shown and/or described herein.

The following table shows by way of example particular values for the potentials of the various batteries and for the impedances of the various resistors and capacitors, in circuits which have been operated successfully. In some cases, the values are also shown in the dravw'ng. These values are set forth by way of example only, and the invention is not limited to them nor to any of them. The diodes are considered to have substantially no impedance in their forward direction and substantially infinite impedance in the reverse direction.

TABLE IFIGS. 1, 5, 8

Triodes 1, 2 (twin triode) Type 5963 Battery 3 volts 30 Battery 4 100 Resistor 5 hms 1.5K Resistors 6, 7 do 6.8K Resistor 9 do 150K Capacitor 10 mmfd 22 Resistor 11 ohms 10K Resistor 13 do 150K Resistor 14 do- 300K Battery 15 volts 150 Resistor 17 ohms 300K Resistor 19 do 75K Resistor 21 do.. 75K Capacitor 23 mmfd 39 FIGS. 5, 8

Battery 49 volts 200 Resistor 50 "ohms" 430K Resistor 51 do 430K Capacitor 52 mrnfd 22 Resistor 53 ohms 0.2K Resistor 58 do 1K Resistor 59 do 1K Resistor 61 do 150K Resistor 63 do 430K Capacitor 70 mfd .01

FIG. 8

Resistor 72 ohrns 75K Resistor 74 do 75K FIG. 11

Triode 90 (twin triode) /2 type 5687 Battery 91 volts 75 Capacitor 92 mrnfd 22 Resistor 93 ohrns 100K FIG. 12

Triodes 102, 103 (twin triode) Type 5687 Battery 104 volts 125 Resistor 105 ohm 0.1K Resistor 106 do .024K Resistor 107 oh 2.0K Resistor 108 do 2.0K Battery 109 volts 75 Battery -.110 do 25 Battery 111 do 25 Resistor 112 nhm 1K Resistor 113 ohms 100K Resistor 114 do 10K Capacitor 115 mmfd S0 Resistor 119 ohm .024K Capacitor 120 mtd .047 Capacitor 121 do .01 Resistor 123 ohm 1.0K Resistor 124 do 0.1K Resistor 125 do 1K Resistor 127 ohms 100K Capacitor 128 mmfd 50 Resistor 129 ohms 200K Battery 130 volts 200 Capacitor 133 mfd .01

FIG. 13

Triode 134 (twin triode) /2 type 5687 Battery 135 volts 150 Resistor 136 ohm 0.1K Resistor 137 do 0.1K Resistor 138 nns-.. 10K Battery 139 volts 100 Resistor 141 s 10K Resistor 143 ohm .024K Battery 144 volts 15 Capacitor 145 mfd .047 Capacitor 146 do .01 Resistor 147 ms" K FIG. 14

Triodes 148, 149 (twin triode) Type 5687 Battery 150 volts 100 Battery 151 do 25 Resistor 152 ohm .024K Resistor 154 do 0.3K Resistor 155 do 0.1K Resistor 156 ohms 10K Resistor 158 do 100K Capacitor 159 mmfd 39 Resistor 160 ohms 200K Battery 161 volts 300 Battery 162 do 150 Resistor 163 nhm 0.1K Resistor 165 do .OMK Resistor 166 volts 15 Capacitor 167 mfd .047 Capacitor 168 do .01 Capacitor 169 do .047 Capacitor 170 do .01

FIG. 15

Triode 172 (twin triode) V2 type 5687 Battery 173 volts 15 Resistor 174 nhms 1.5K Resistor 175 ohm 0.1K Battery 176 volts 100 Resistor 178 ohms 100K Capacitor 1'79 mmfd 39 Resistor 180 "ohms-.. 200K Battery 181 volts 300 Capacitor 183 mfd .01

While I have shown and described certain preferred embodiments of my invention, other modifications thereof will readily occur to those skilled in the art, and I there- 17 fore intend my invention to be limited only by the appended claims.

I claim:

1. A shifting register, comprising a plurality of electrical triggers connected in cascade, each trigger being shiftable between two alternate conductive conditions to register the presence or absence of a binary quantity, and means for shifting the register to produce in each trigger the conductive condition previously existing in the preceding trigger in the cascade, said shifting means comprising, for each trigger, gate means for comparing the conductive condition of the trigger with that of the preceding trigger, synchronizing means for supplying bipolar shifting pulses, including two pulse lines for respectively supplying positive-going and negative-going synchronous square wave signals to the gate means of all the triggers, said signals having the same signal potential and unequal no-signal potentials of opposite polarities, said gate means being effective to block all said shifting pulses from the triggers which are in the same conductive states as their respective preceding triggers, to admit a positive-going shifting pulse to each trigger which is in one of said two states and whose preceding trigger is in the other conductive state, and to admit a negative-going shifting pulse to each trigger which is in the other of said two conductive states and whose preceding trigger is in said one conductive state.

2. A shifting register comprising a plurality of bistable triggers, each having an input terminal and direct and complementary output terminals; a plurality of comparison gate means, each connecting a trigger with a following trigger and including two resistors connected in series between the direct output terminal of one trigger and the complementary output terminal of the following trigger; synchronizing pulse means comprising a source of positive-going pulses shiftable between a predetermined potential and a more negative background potential, a source of negative-going signal pulses synchronized with said source of positive-going pulses and shiftable between said predetermined potential and a more positive background potential, and two diodes connecting the respective pulse sources to the common terminal of the two series-connected resistors; and a capacitor coupling said common terminal to the input terminal of the following trigger.

3. A shifting register comprising a plurality of bistable trigger units, each unit comprising a bistable trigger having an input terminal and direct and complementary output terminals, shiftable between signal and no signal potentials, the no-signal potential of the complementary terminal being equal to the signal potential of the direct output terminal, and a plurality of input gate means; a plurality of signal entry terminals, each shiftable between signal and no-signal potentials equal to the respective potentials of the direct output terminal; each said input gate means connecting one signal entry terminal to the trigger input terminal and comprising two resistors connected in series between the signal entry terminal and the complementary output terminal of the trigger, a capacitor coupling the common terminal of the two resistors to the input terminal of the trigger, and synchronizing pulse means comprising a source of positive-going pulses shiftable between a predetermined potential and a more negative background potential, a source of negative-going signal pulses synchronized with said source of positivegoing pulses and shiftable between said predetermined potential and a more positive background potential, and two diodes connecting the respective pulse sources to the common terminal of the two series-connected resistors; said diodes being poled to oppose current flow between said sources at said background potentials and cooperating with said pulse sources when the sources are at their background potentials to open the gate means so that the potential of the common terminal is determined by the potential of the signal entry terminal, the potential of the complementary output terminal and the two resistors; said diodes being eifective when said pulse sources are at said predetermined potential to clamp said common terminal at said predetermined potential, thereby closing the gate means; and means for selectively clamping the pulse sources of all the gate means but one at said predetermined potential, so that the signal entry terminal connected to the one gate means determines the operation of the trigger between its stable states.

4. A shifting register, comprising a plurality of electrical triggers connected in cascade, each trigger being shiftable between two alternate conductive conditions to register the presence or absence of a binary quantity, means for shifting the register to produce in each trigger the conductive condition previously existing in the preceding trigger in the cascade, said shifting means comprising, for each trigger, gate means for comparing the conductive condition of the trigger with that of the preceding trigger, synchronizing means connected to the gate means of all the triggers for supplying shifting pulses to all the gate means simultaneously, said synchronizing means comprising two pulse lines and means for supplying to the respective pulse lines synchronous positivegoing and negative-going square wave signal pulses having equal signal potentials and unequal no-signal potentials of opposite polarity, and a pair of oppositely poled diodes connecting said pulse lines to a common junction in said gate means, said diodes being poled reversely with respect to the no-signal potentials of said pulse lines, said diodes and pulse lines being effective during said square wave signals to clamp said junction at said signal potential, said gate means being effective to block said shifting pulses from the triggers which are in the same conductive states as their respective preceding triggers, and to admit said shifting pulses to the triggers which are in conductive states opposite to the states of the preceding triggers, and clamp means for terminating said shifting pulses and supplying continuously to said pulse lines said signal potential and thereby to render the conductive condition of each trigger independent of the conductive condition of the other triggers.

5. A shifting register comprising a plurality of electrical triggers connected in cascade, each trigger being shiftable between two alternate stable conductive conditions which respectively register the presence and absence of a binary quantity each trigger having complementary direct and inverse outputs which shift in opposite senses between two separated potential magnitudes as the trigger shifts between its two stable conditions, means for shifting the register to produce in each following trigger the conductive condition previously existing in the preceding trigger of the cascade, said shifting means including voltage divider means for comparing the conductive condition of each pair of preceding and following triggers including a first impedance connected between one output of the preceding trigger and a junction, a second impedance connected between said junction and the complementary output of the following trigger, said impedances cooperating with said preceding and following triggers to hold said junction at one or the other of said two potential magnitudes when said triggers are in opposite conditions and to hold said junction at a third magnitude intermediate between said two magnitudes when said triggers are in the same conductive condition, and synchronizing means connected to the common junctions of all the triggers for supplying shifting pulses to all said common junctions simultaneously, said synchronizing means including two pulse lines for respectively supplying positive-going and negative-going synchronized signals having signal potentials equal tosaid third magnitude and unequal no-signal potentials of opposite polarity, and two oppositely poled diodes connecting said pulse lines to said junction, said diodes being poled reversely with respect to the no-signal potentials of said pulse lines, said diodes and pulse lines being effective during said square wave signals to clamp said junction at said signal potential, and means coupling the junction of each trigger to a trigger input eflective in response to an input signal to shift the trigger from one conductive condition to the other, said voltage divider means and said diodes cooperating when said preceding and following triggers are in the same condition to block said signal pulses from the coupling means, and cooperating when said preceding and following triggers are in different conditions to pass said signal pulses to said coupling means and thereby to shift the following trigger to the state of the preceding trigger.

6. A shifting register as defined in claim 5, in which each said trigger comprises a pair of electric translating devices, each having an input electrode, an output electrode, and a common electrode, means cross-coupling the output electrode of each device to the input electrode of the other device, said cross-coupling means being effective when one device is conducting to hold the other cut 01f, and said coupling means connects said junction to one of said input electrodes, said one input electrode being effective in response to input signals of opposite polarities to switch its associated trigger between its two conditions in opposite senses.

References Cited in the file of this patent UNITED STATES PATENTS 2,535,303 Lewis Dec. 26, 1950 20 r 2,557,729 Eckert June 19, 1951 2,560,751 Trousdale July 17, 1951 2,580,771 Harper Jan. 1, 1952 2,594,731 Connolly Apr. 29, 1952 2,628,309 Hughes Feb. 10, 1953 2,633,528 Hutson Mar. 31, 1953 2,647,999 Best Aug. 4, 1953 2,666,575 Edwards Ian. 19, 1954 2,688,078 Bess Aug. 31, 1954 2,700,502 Hamilton Jan. 25, 1955 2,706,811 Steele Apr. 19, 1955 2,719,228 Auerbach et a1 Sept. 27, 1955 2,734,684 Ross et al. Feb. 14, 1956 2,781,447 Lester Feb. 12, 1957 2,785,304 Bruce et a1. Mar. 12, 1957 2,802,940 Burton Aug. 13, 1957 2,808,203 Geyer et a1. Oct. 1, 1957 2,816,226 Forrest et a1. Dec. 10, 1957 2,819,840 Huntley et a1. Jan. 14, 1958 2,876,365 Slusser Mar. 3, 1959 OTHER REFERENCES De Turk: Basic Circuitry of the Midac and Midsac, University of Michigan Engineering Research Institute (Ypsilanti), May 1954, pp. II8 and II9.

High-Speed Computing Devices, Engineering Research Associates. Published by McGraw-Hill (New York), 1950, pp. 297 to 299, FIGS. 13-24. 

